The evolution of the computer integrated chip (IC) has been driven by the need to increase speed, performance, and functionality. The successful achievement of these objectives has required a radical change in chip architecture with the introduction of multilevel interconnect schemes which exploit the third (vertical) dimension in the chip in order to enhance device performance. This approach simultaneously minimizes any increase in overall interconnect line lengths and in chip size, or "real estate." These multilevel interconnect schemes are expected to average up to seven levels of interconnects within the next decade in what is commonly referred to as ultra-large scale integration (ULSI).
The changes in chip architecture have been accompanied by a continuing decrease in single device feature size in order to accommodate more devices per chip, leading to appreciable enhancement in chip functionality. In this respect, device features are expected to shrink from a nominal 0.5 .mu.m today to less than 0.18 .mu.m by the year 2000. However, the trend in decreasing feature size has encountered serious performance problems in terms of increased RC delay, where R is the resistance and C the capacitance, in interconnect structures.
Significant reduction in line resistance R could be achieved by replacing currently used metallization architecture, which consists of tungsten plugs and tungsten or aluminum interconnects, with a fully integrated copper based metallization scheme. Copper exhibits lower resistivity (bulk resistivity=1.68 .mu.-ohm-cm) than aluminum and tungsten, which should yield up to 40% reduction in RC delay. It is also predicted to display enhanced electromigration and stress resistance, thus leading to higher reliability and improved performance.
However, a major problem in the realization of such structurally-stable, copper-based metallization architectures is the identification of an appropriate diffusion barrier and adhesion promoter which provides the performance required in sub-quarter-micron device technologies. Copper is known to be highly reactive with and a fast diffuser in silicon. Its presence in silicon leads to the formation of deep trap levels which ruin device performance. Currently titanium and titanium nitride technology is used, but is not expected to deliver the performance required, given the need for increasingly thinner liners, in order to maximize space availability for the actual conductor in the continuously shrinking device structures. Additionally, adhesion of copper to prior art titanium nitride diffusion barriers and adhesion promoters has been known to be problematic, especially if the titanium nitride has been exposed to air prior to the copper deposition step.
Tantalum-based compounds provide a potential solution to these problems. Tantalum and its binary and ternary nitrides are highly refractory materials which are stable to extremely high temperatures and which are known to be non-reactive with copper. Copper-tantalum contacts have a demonstrated stability up to 550.degree. C., with the motion of copper being extremely slow through tantalum at the typical temperatures used in microelectronic device fabrication. Additionally, tantalum-based nitrides have even higher melting points than tantalum. Tantalum nitrides exhibit high melting points, for example, TaN and Ta.sub.2 N have melting points of 2050.degree. C. and 3087.degree. C., respectively. These properties have led to the successful demonstration of sputtered tantalum nitrides as good diffusion barriers for copper-based technology, with proven copper-tantalum contact stability to temperatures as high as 750.degree. C.
More importantly, the need for increasingly thinner liners make tantalum-based alloys inherently more desirable than their titanium counterparts. This may be because tantalum is a heavier (larger) ion than titanium, and accordingly tantalum-based alloys should provide the diffusion barrier performance required in ULSI structures at liner thicknesses which are significantly reduced in comparison with those of titanium alloys. The enhanced performance at reduced liner thicknesses ensures maximization of the useful space available for aluminum or copper conductors in the continuously shrinking device structures.
In this respect, ternary tantalum alloys, such as TaN.sub.x Si.sub.y, where x is greater than 0 and less than or equal to 2 and y is greater than 0 and less than or equal to 3, might be highly desirable in view of their unique structural properties. Not only do these compounds share the excellent diffusion barrier characteristics of their binary tantalum counterparts, but they also could be grown in amorphous form. The formation of the amorphous phase would eliminate the existence of grain boundaries, thereby preventing any potential metal, e.g. copper, diffusion pathways along such boundaries, and enhancing the barrier properties of the resulting TaN.sub.x Si.sub.y phase.
One important application of pure tantalum is its ability to getter oxygen. As such, it provides a stable ohmic contact when deposited directly on silicon and alloyed to it to form a tantalum silicide, TaSi.sub.y, phase with y being greater than zero and possibly less than or equal to 3. Traditionally, the formation of the tantalum silicide phase involves the deposition of pure tantalum on silicon, then either a single anneal or multiple anneals at high temperature (as high as 900.degree. C.) to form the silicide phase. However, as semiconductor device sizes become smaller than a quarter of a micron, the consumption of silicon from the substrate in the silicidation process becomes highly undesirable and quite problematic, leading to contact reliability concerns, as well as possible current leakage and device performance issues. Clearly, a need exists for the development of deposition processes for the growth of tantalum silicide directly from the vapor phase, without the need for silicon consumption from the underlying substrate.
At present, tantalum and its binary and ternary nitrides are grown by conventional sputtering techniques. These techniques, unfortunately, are inherently incapable of conformal step coverage in aggressive trench and via structures, given their line of sight approach to metal deposition. Therefore, alternate processing techniques are required for growing tantalum-based films for applications in sub-quarter-micron devices. In this respect, chemical vapor deposition (CVD) is one of the most promising techniques. CVD displays an intrinsic potential for conformal coverage of aggressive via and hole structures, in view of its ability to use the substrate surface as a catalyst for the deposition reaction. In addition, CVD has a proven ability to deposit pure and doped materials at industrially viable growth rates over large substrate areas, such as a standard 200 mm wafer size which is currently used in the semiconductor industry.
Numerous CVD approaches have already been tested for the growth of tantalum and its nitrides. Inorganic CVD using tantalum pentachloride (TaCl.sub.5) in a hydrogen, nitrogen, and argon atmosphere led to the deposition of TaN and Ta.sub.2 N at temperatures in the range of 700-1000.degree. C. See T. Takahashi, H. Itoh, and S. Ozeki, J., Less-Common Met. vol. 52, 29 (1977). Clearly, the high processing temperatures required prohibit the use of this deposition methodology in actual semiconductor devices. The high temperature is required to ensure complete dissociation of the tantalum-chlorine bonds in TaCl.sub.5, and the subsequent reaction with ammonia to produce the nitride phase. Clearly, these high processing temperatures prohibit the use of such a CVD tantalum pentachloride-based deposition methodology in actual semiconductor devices. In addition, the inclusion of small amounts of chlorine (up to 5 at %) in the tantalum-based films is highly problematic, given chlorine's mobility out of the resulting nitride phase and into the surrounding layers, which causes significant corrosion and reliability problems.
Organometallic CVD approaches have been attempted which include the use of homoleptic dialkylamido tantalum complexes, and tributyldiethyl tantalum type sources. See S. C. Sun, M. H. Tsai, H. T. Chiu, S. H. Chuang, and C. E. Tsai, Proceedings of the IEDM; S. C. Sun, M. H. Tsai, C. E. Tsai, and H. T. Chiu, Proceedings of the 12th International VLSI Multilevel Interconnection Conference (VMIC, Tampa, Fla., 1995) p. 157; and R. Fix, R. G. Gordon, and D. M. Hoffman, Chem. Mater. vol. 5, 614 (1993). However, the organometallic CVD-based deposition methods did not encounter much success for a variety of reasons. In the case of tantalum, the organometallic CVD route was unable to produce pure tantalum films which were free of carbon and oxygen contaminants. In the case of nitrides, the low vapor pressure of the sources used in some cases made the resulting organometallic CVD process production unworthy, while the relative instability and short shelf life of the precursors used in some other cases created difficulties in transport, handling and storage.
However, none of the above approaches has led to the identification of an organometallic CVD process suitable for manufacturing which incorporates tantalum and its various nitrides and alloys into ULSI computer device structures.
Therefore, a critical need in the art exists for a method for providing tantalum- and tantalum-based films, preferably which are suitable for ULSI fabrication in manufacturing. A need in the art exists for tantalum-based films of an electronic grade, i.e., of an especially ultra-high quality, in terms of purity, with impurity concentrations well below 1 at %, which exhibit a non-columnar structure to perform appropriately as a barrier layer, and which are conformal to the complex topography of ULSI circuitry.
There is further a need in the art for a method which can readily prepare single films consisting of either pure tantalum, or tantalum-based films such as tantalum nitrides or bilayer or films which include appropriately dimensioned films of tantalum and its various alloys. There is also a need for a method which is amenable to process temperatures below about 675.degree. C., and preferably below about 500.degree. C. to prevent thermally induced damage to the device during processing.
There is also a need in the art for a process which allows for the preparation of the above-mentioned films sequentially and in situ, i.e., without the necessity of exposing a substrate coated with a tantalum-based film(s) to air during transport to another reaction chamber to deposit further film(s). According to prior art methods, the production of bilayer or multilayer structures typically involves the laying down of a first layer in a first reaction chamber, and then transferring the substrate to a different reaction chamber(s) where the subsequent layer(s) are coated onto the already grown layer(s) in a fashion which typically exposes the substrate to air. The prior art processes do not provide a single reaction chamber with the versatility to deposit tantalum and its nitrides merely by controlling the operating parameters of the chamber. The prior art also does not provide for the deposition of tantalum and/or its nitrides in two or more chambers interconnected by vacuum load locks or central handlers which allow sample transfer between reactors without exposure to air.
In particular, a process for the in situ deposition of sequential bilayers or multilayers of tantalum and its nitrides is desirable, in part, because of the high affinity of tantalum for oxygen and water. This affinity leads typically to contamination of the tantalum-based film surface during transfer to a second reaction chamber where it is coated with the subsequent layer(s) in a manner which exposes the layers to air.